An 8T Low-Voltage and Low-Leakage Half-Selection Disturb-Free SRAM Using Bulk-CMOS and FinFETs

An 8T Low-Voltage and Low-Leakage Half-Selection Disturb-Free SRAM Using Bulk-CMOS and FinFETs

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This product is an 8T SRAM cell design using Bulk-CMOS and FinFETs, aiming to reduce leakage power and improve operational efficiency.

  • The description claims a 58% improvement in write power and 67% in read power per operation compared to a conventional 6T SRAM cell.
  • The description claims an improvement of 2.08 μ in read static noise margin at VDD=1.0 V when using FinFETs.

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